Rethinking Scan Chains In Semiconductor Test

Rethinking Scan Chains In Semiconductor Test

An explosion in design complexity, fueled by increased transistor density and fundamental shifts in chip architectures, are beginning to overwhelm traditional approaches to test. Defects can show up in the clock trees that drive scan chains, and even inside blocks of scan cells, which may number in the millions. Jayant D’Souza, technical product director for yield learning products in Siemens EDA’s Tessent group, talks about how the shift to bac…