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We’ve discovered 287 headlines written by Semiconductor Engineering during the past 3 months.

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Top Semiconductor Engineering News

Wisconsin Politics · Madison

Wisconsin Supreme Court Delivers Win for Environmentalists in Fight over ‘Forever Chemicals’

60% Center coverage: 73 sources

See the Story

Trade War · United States

U.S. lifts chip software curbs on China amid trade truce

56% Center coverage: 63 sources

See the Story

Semiconductors

ASU Selected as Home and Partner for CHIPS Act - Arizona PBS

100% Left coverage: 1 sources

ASU has been selected as the home and partner for the CHIPS and Science Act-funded national lab for semiconductor advanced packaging.See the Story

Framework To Analyze Threats To The Semiconductor Supply Chain (NIST, U. Of Maryland) - Data Intelligence

A new technical paper titled “Analyzing Collusion Threats in the Semiconductor Supply Chain” was published by researchers at NIST and University of Maryland. Abstract“This work proposes a framework for analyzing threats related to the semiconductor supply chain. The framework introduces a metric that quantifies the severity of different threats subjected to a collusion of adversaries from different stages of the supply chain. Two different case …Gaithersburg · Gaithersburg See the Story

Development And Deployment Of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel) - Data Intelligence

A new technical paper titled “System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution” was published by researchers at Intel Corporation. Abstract“The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigates the complexities of realizing large-scale chiplet syst…New York State · New York See the Story

Rethinking Scan Chains In Semiconductor Test

An explosion in design complexity, fueled by increased transistor density and fundamental shifts in chip architectures, are beginning to overwhelm traditional approaches to test. Defects can show up in the clock trees that drive scan chains, and even inside blocks of scan cells, which may number in the millions. Jayant D’Souza, technical product director for yield learning products in Siemens EDA’s Tessent group, talks about how the shift to bac…Read Article

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)

A new technical paper titled “FastPath: A Hybrid Approach for Efficient Hardware Security Verification” was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. Abstract “Many verification methods have been proposed to detect microarchitectural information leakage in response to the surge of security breaches in hardware designs. These sophisticated efforts have gone a long way toward preventing attackers from breaking the sy…Kaiserslautern · Kaiserslautern Read Article

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich Et Al.) - Data Intelligence

A technical paper titled “Data-driven power modeling and monitoring via hardware performance counter tracking” was published by researchers at ETH Zürich, Scuola Superiore Sant’Anna, RISE Research Institutes of Sweden and University of Bologna. Abstract“Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an affordable power budget, often under real-time constraints. Hardwar…Switzerland · Switzerland See the Story

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech) - Data Intelligence

A new technical paper titled “CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms” was published by Georgia Tech. Abstract“In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth), which require the delivery of operands at a cadence de…Atlanta, Georgia · Atlanta See the Story

High-Performance p-type 2D FETs By Nitric Oxide Doping (Penn State)

A new technical paper titled “High-performance p-type bilayer WSe2 field effect transistors by nitric oxide doping” was published by researchers at Penn State University and Florida International University. Abstract “Two-dimensional (2D) materials are promising candidates for next-generation electronics, but the realization of high-performance p-type 2D field-effect transistors (FETs) has remained challenging, hindering the development of fully…Pennsylvania · Pennsylvania Read Article

Research Bits: July 1

Copper-to-copper bonding for GaN integration Researchers from MIT, Georgia Tech, and Air Force Research Laboratory propose a bonding process to integrate gallium nitride (GaN) transistors onto standard silicon CMOS chips. They used the process to create a power amplifier. “We wanted to combine the functionality of GaN with the power of digital chips made of silicon, but without having to compromise on either cost of bandwidth. We achieved that b…Pennsylvania · Pennsylvania Read Article

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Top Semiconductor Engineering News

Wisconsin Supreme Court Delivers Win for Environmentalists in Fight over ‘Forever Chemicals’

U.S. lifts chip software curbs on China amid trade truce

ASU Selected as Home and Partner for CHIPS Act - Arizona PBS

Framework To Analyze Threats To The Semiconductor Supply Chain (NIST, U. Of Maryland) - Data Intelligence

Development And Deployment Of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel) - Data Intelligence

Rethinking Scan Chains In Semiconductor Test

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich Et Al.) - Data Intelligence

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech) - Data Intelligence

High-Performance p-type 2D FETs By Nitric Oxide Doping (Penn State)

Research Bits: July 1

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