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Imec Unveils 7‑bit, 175GS/s Massively Time-Interleaved Slope-ADC
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Imec unveils 7‑bit, 175GS/s massively time-interleaved slope- ADC – pairing record-small footprint and low conversion energy with top sampling speed
At IEEE ISSCC 2026, imec introduces a 7-bit, 175GS/s wireline ADC implemented in 5nm FinFET technology, combining a record-small footprint (250 x 250µm²) and low conversion energy (2.2 pJ per sample). The design builds on the massively time–interleaved slope–ADC architecture imec debuted in 2024, now enhanced with patented linearization and switched input buffer techniques to ensure precise signal conversion and wide bandwidth at ultra-high samp…
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