Simulation Study Of Vertically Stacked 2D NSFETs

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Simulation Study Of Vertically Stacked 2D NSFETs

A new technical paper titled “Simulation of Vertically Stacked 2-D Nanosheet FETs” was published by researchers at Università di Pisa and TU Wien. Abstract “We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet FET at the ultimate nanosheet thickness, using 2-D mater…