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Samsung Reveals Next-Gen Memory with Stacked HBM and 400-Layer NAND

The roadmap centers on zHBM and V10 BV-NAND, with Samsung saying the new memory designs can boost density and efficiency for AI systems.

  • At the Future of Memory and Storage 2026 conference in Santa Clara, California, Samsung unveiled a roadmap featuring Bonding V-NAND architecture with more than 400 layers, vertically stacked High Bandwidth Memory, and a next-generation NAND approach.
  • Thirteen years after introducing its first V-NAND technology, Samsung unveiled V10 BV-NAND, which boosts memory density by about 58% over the previous generation using wafer bonding to stack more than 400 layers.
  • Samsung also introduced a new High Bandwidth Memory concept that stacks memory directly on processors, achieving more than 10 times the density of HBM5 while improving energy efficiency threefold and cutting thermal resistance.
  • The company showcased a next-generation NAND approach for edge applications alongside its LPDDR5X-PIM memory chip, which features Processing-In-Memory to perform computations within memory before sending results to the processor.
  • Executives Jin-Yub Lee and Kyungryun Kim presented the keynote titled "Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture," detailing how these technologies target large-scale training workloads in data centers and edge applications.
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(Seoul = Yonhap News) Reporter Kang Tae-woo = Samsung Electronics [discussed] next-generation memory technology at the 'FMS Awards' held during the global memory technology conference 'FMS 2026'.

·Seoul, Korea (the Republic of)
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Business Wire broke the news in Crystal River, United States on Tuesday, August 4, 2026.
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