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TSMC Prepares "CoPoS": Next-Gen 310 × 310 Mm Packages
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At TSMC, the CoWoS (Chip-on-Wafer-on-Substrate) technology has been in place for several years. But contrary to what you do methodically every night in your kitchen, i.e. reuse the drops of your carefully cut-out preparations, it is more complicated to make the circular wafers profitable when you take rectangular modules: this geometric constraint hinders optimization...
TSMC Prepares "CoPoS": Next-Gen 310 × 310 mm Packages
As demand for ever-growing AI compute power continues to rise and manufacturing advanced nodes becomes more difficult, packaging is undergoing its golden era of development. Today's advanced accelerators often rely on TSMC's CoWoS modules, which are built on wafer cuts measuring no more than 120 × 150 mm in size. In response to the need for more space, TSMC has unveiled plans for CoPoS, or "Chips on Panel on Substrate," which could expand substr…
One, two, four compute chips, up to 12 HBM4 chips and other I/O chips are the requirements for packaging technologies in the coming years.
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